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Archadian Sdn Bhd

Logic Design and Design Verification Engineer

Archadian Sdn Bhd Posted: 3 Month
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Description:

 - Performs IP block logic design, RTL coding, simulation and verification
- Analyses the performance bottleneck of existing solutions, and devise new algorithms and structures to improve the performance, area and power.
- Writes micro-architecture specification documentation, and work with the design team to implement the next generation design using industry-leading process nodes
- Defines and creates test plans for RTL validation, develop coverage-driven system verilog/UVM test benches
- Runs both RTL and gate-level simulations and regressions, debug and implement corrective measures for failing tests
- Capacity could include full chip/system functional verification (defining verification strategies, methodologies and test plan to enable effective verification).
- Works with design engineers to perform logic synthesis and equivalence check.
- Collaborates with design engineers of other discipline on the overall IP implementation.
- Mentors and coaches junior engineers as appropriate
- Have strong fundamental knowledge in high speed data transport industry standard specification, and have extensive coding experience that includes logic+behavioral modelling, complex state machine, and high speed logic optimizations.
- Able to code RTL design and verification with Verilog / System Verilog.
- Experienced in pre-silicon verification using high speed industry standard specification and protocols
- Ability to debug and resolve complex bugs independently.
- Able to interpret, analyse report and provide solution to complex problems.
- Possess cross-discipline knowledge in Analog integration, RTL/System Verilog, static timing analysis concepts, floor-planning, design specifications
- Knowledge of digital design methodologies, low latency design and tool flow (CDC, LINT, UPF, or GLS) is an added advantage.
- Experience with industry standard tools for design such as VCS, Xcelium, synthesis tool etc is an added advantage.
- Knowledge in Python Perl, TCL, C-shell scripting will be an added advantage
Note: Salary is base on experience


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